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integrated circuit systems, inc. general description features ics9248- 81i advance information 0851?08/06/03 block diagram frequency generator & integrated buffers pin configuration generates the following system clocks: - 3 cpu(2.5v/3.3v) up to 133.3mhz. - 6 pci(3.3v) (including 1 free-running) - 13 sdrams(3.3v) up to 133.3mhz. - 3 ref (3.3v) @ 14.318mhz - 1 clock @ 24/14.3 mhz selectable output for sio - 1 fixed clock at 48mhz (3.3v) - 1 ioapic @ 2.5v / 3.3v skew characteristics: - cpu ? cpu<175ps - sdram ? sdram < 250ps - cpu?sdram < 500ps - cpu(early) ? pci : 1-4ns (typ. 3ns) - pci ? pci <500ps supports spread spectrum modulation 0.25 & 0.5% center spread serial i 2 c interface for power management, frequency select, spread spectrum. efficient power management scheme through pci, sdram, cpu stop clocks and pd#. uses external 14.318mhz crystal 48 pin 300mil ssop. 48-pin ssop power groups vddref = ref [2:0], x1, x2 vddpci = pciclk_f, pciclk [4:0] vddsd/c = sdram [11:0], supply for pll core, 24 mhz, 48mhz vdd/cpu = cpuclk [3:1] vddlapic = ioapic gndfix = ground for fixed clock pll and output buffers * internal pull-up resistor of 120k to 3.3v on indicated inputs the ics9248-81i is the single chip clock solution for desktop/notebook designs using the sis style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248- 81i employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. the sd_sel latched input allows the sdram frequency to follow the cpuclk frequency(sd_sel=1) or other clock frequencies (sd_sel=0) advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. i
2 ics9248 -81i advance information 0851?08/06/03 pin descriptions notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. pin number pin name type description 1 vddr/x power isolated 3.3 v power for crystal & reference ref0 output 3.3v, 14.318 mhz reference clock output. mode input function select pin, 1=desk top mode, 0=mobile mode. latched input. 3,9,16,22, 27,33,39 gnd power 3.3 v ground 4 x1 input 14.318 mhz crystal input 5 x2 output 14.318 mhz crystal output 6,14 vddpci power 3.3 v power for the pci clock outputs fs1 input logic input frequency select bit. input latched at power-on. pciclk_f output 3.3 v free running pci clock output, will not be stopped by the pci_stop# pciclk 0 output 3.3 v pci clock outputs, generating timing requirements for pentium ii fs2 input logic input frequency select bit. input latched at power-on. 13, 12, 11, 10 pciclk [4:1] output 3.3 v pci clock outputs, generating timing requirements for pentium ii 15,28,29,31,32, 34,35,37,38 sdram 12, sdram [7:0] output sdram clock outputs. frequency is selected by sd-sel latched input. sdram 11 output sdram clock outputs. frequency is selected by sd-sel latched input. cpu_stop# input asynchronous active low input pin used to stop the cpuclk in low state, all other clocks will conti nue to run. the cpuclk will have a "turnon" latency of at least 3 cpu clocks. sdram 10 output sdram clock outputs. frequency is selected by sd-sel latched input. pci-stop# input synchronous active low input used to stop the pciclk in a low state. it will not effect pciclk_f or any other outputs. 19 vddsd/c power 3.3 v power for sdram outputs and core sdram 9 output sdram clock outputs. frequency is selected by sd-sel latched input. sdram_stop# input asynchronous active low input used to stop the sdram in a low state. it will not effect any other outputs. sdram 8 output sdram clock outputs. frequency is selected by sd-sel latched input. pd# input asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 3ms. 23 sdata input data input for i 2 c serial input. 24 sclk input clock input of i 2 c input sel24_14# input this input pin controls the frequency of the sio. if logic 0 at power on sio=14.318 mhz . if logic 1 at power-on sio=24mhz. sio output super i/o output. 24 or 14.318 mhz. selectable at power-up by sel24_14mhz fs0 input logic input frequency select bit. input latched at power-on. 48 mhz output 3.3 v 48 mhz clock output, fixed frequency clock typically used with usb devices 30,36 vddsdr power 3.3 v power for sdram outputs 40,41,43 cpuclk [3:1] 0utput 2.5 v cpu and host clock outputs 42 vddlcpu power 2.5 v power for cpu ref2 output 3.3v, 14.318 mhz reference clock output. cpu3.3#_2.5 input this pin selects the operating voltage for the cpu. if logic 0 at power on cpu=3.3 v and if logic 1 at power on cpu=2.5 v operating voltage. 45 gndl power 2.5 v ground for the ioapic or cpu ref1 output 3.3v, 14.318 mhz reference clock output. sd_sel input this input pin controls the frequency of the sdram. 47 ioapic output 2.5v fixed 14.318 mhz ioapic clock outputs 48 vddlapic power 2.5 v power for ioapic 2 1,2 8 1,2 26 1,2 7 1,2 46 1,2 44 1,2 17 1 20 1 18 1 21 1 25 1,2
3 ics9248-81i advance information 0851?08/06/03 power management functionality mode pin - power management input control cpu 3.3#_2.5v buffer selector for cpuclk drivers. pd# cpu_stop# pci_stop# sdram_stop pciclk (0:4) sdram (0:12) pciclk_f cpuclk crystal osc vco 0x x x stopped low stopped low stopped low stopped low stopped low stopped low 1 1 1 1 running running running running running running 1 1 1 0 running stopped low running running running running 11 0 1 stopped low running running running running running 11 0 0 stopped low stopped low running running running running 1 0 1 1 running running running stopped low running running 1 0 1 0 running stopped low running stopped low running running 10 0 1 stopped low running running stopped low running running 10 0 0 stopped low stopped low running stopped low running running 2 n i p , e d o m ) t u p n i d e h c t a l ( 7 1 n i p8 1 n i p0 2 n i p1 2 n i p 0 # p o t s _ u p c ) t u p n i ( # p o t s _ i c p ) t u p n i ( # p o t s _ m a r d s ) t u p n i ( # d p ) t u p n i ( 1 1 1 m a r d s ) t u p t u o ( 0 1 m a r d s ) t u p t u o ( 9 m a r d s ) t u p t u o ( 8 m a r d s ) t u p t u o ( 5 . 2 _ # 3 . 3 u p c l e v e l t u p n i ) a t a d d e h c t a l ( d e t c e l e s r e f f u b n o i t a r e p o r o f : t a 1d d v v 5 . 2 0d d v v 3 . 3
4 ics9248 -81i advance information 0851?08/06/03 functionality v dd 1, 2, 3, 4 = 3.3v5%, v ddl = 2.5v 5% or 3.3 5%, ta= 0 to 70c crystal (x1, x2) = 14.31818mhz sd_sel fs2 fs1 fs0 cpu mhz sdram mhz pci mhz ref, ioapic mhz 0 0 0 0 90.00 90.00 30.00 14.318 0 0 0 1 66.70 100.05 33.35 14.318 0 0 1 0 95.00 63.33 31.66 14.318 0 0 1 1 100.00 66.66 33.33 14.318 0 1 0 0 100.00 75.00 30.00 14.318 0 1 0 1 112.00 74.66 37.33 14.318 0 1 1 0 124.00 82.66 31.00 14.318 0 1 1 1 133.30 88.86 33.32 14.318 1 0 0 0 66.70 66.70 33.35 14.318 1 0 0 1 75.00 75.00 30.00 14.318 1 0 1 0 83.30 83.30 33.32 14.318 1 0 1 1 95.00 95.00 31.66 14.318 1 1 0 0 100.00 100.00 33.33 14.318 1 1 0 1 112.00 112.00 37.33 14.318 1 1 1 0 124.00 124.00 31.00 14.318 1 1 1 1 133.30 133.30 33.33 14.318
5 ics9248-81i advance information 0851?08/06/03 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
6 ics9248 -81i advance information 0851?08/06/03 byte 0: functionality and frequency select register (default = 0) serial configuration command bitmap note 1: default at power-up will be for latched logic inputs to define frequency. note 2: pwd = power-up default t i b n o i t p i r c s e d d w p 7 t i b m u r t c e p s d a e r p s r e t n e c % 5 2 . 0 - 0 1 m u r t c e p s d a e r p s r e t n e c % 5 . 0 - 1 t i b ) 4 : 6 , 2 ( ) 4 : 6 , 2 ( t i bk l c u p cm a r d sk l c i c p x x x x 1 e t o n 0 0 0 00 0 . 0 90 0 . 0 90 0 . 0 3 1 0 0 00 7 . 6 65 0 . 0 0 15 3 . 3 3 0 1 0 00 0 . 5 93 3 . 3 66 6 . 1 3 1 1 0 00 0 . 0 0 16 6 . 6 63 3 . 3 3 0 0 1 00 0 . 0 0 10 0 . 5 70 0 . 0 3 1 0 1 00 0 . 2 1 16 6 . 4 73 3 . 7 3 0 1 1 00 0 . 4 2 16 6 . 2 80 0 . 1 3 1 1 1 00 3 . 3 3 16 8 . 8 82 3 . 3 3 0 0 0 10 7 . 6 60 7 . 6 65 3 . 3 3 1 0 0 10 0 . 5 70 0 . 5 70 0 . 0 3 0 1 0 10 3 . 3 80 3 . 3 82 3 . 3 3 1 1 0 10 0 . 5 90 0 . 5 96 6 . 1 3 0 0 1 10 0 . 0 0 10 0 . 0 0 13 3 . 3 3 1 0 1 10 0 . 2 1 10 0 . 2 1 13 3 . 7 3 0 1 1 10 0 . 4 2 10 0 . 4 2 10 0 . 1 3 1 1 1 10 3 . 3 3 10 3 . 3 3 13 3 . 3 3 3 t i b d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 s t u p n i 4 : 6 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
7 ics9248-81i advance information 0851?08/06/03 byte 1: cpu, active/inactive register (1 = enable, 0 = disable) byte 2: pci active/inactive register (1 = enable, 0 = disable) byte 3: sdram active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. byte 4: sdram active/inactive register (1 = enable, 0 = disable) byte 5: peripheral active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 3 k l c u p c 2 t i b1 41 2 k l c u p c 1 t i b3 41 1 k l c u p c 0 t i b-x# 0 s f t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 1 s f 6 t i b71 f _ k l c i c p 5 t i b-1 ) d e v r e s e r ( 4 t i b3 11 4 k l c i c p 3 t i b2 11 3 k l c i c p 2 t i b1 11 2 k l c i c p 1 t i b0 11 1 k l c i c p 0 t i b81 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b8 21 7 m a r d s 6 t i b9 21 6 m a r d s 5 t i b1 31 5 m a r d s 4 t i b2 31 4 m a r d s 3 t i b4 31 3 m a r d s 2 t i b5 31 2 m a r d s 1 t i b7 31 1 m a r d s 0 t i b8 31 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-x# 2 s f 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 c i p a o i 3 t i b-x # l e s _ d s 2 t i b4 412 f e r 1 t i b6 411 f e r 0 t i b210 f e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b5 21 z h m 4 1 / 4 2 5 t i b6 21 z h m 8 4 4 t i b5 11 2 1 m a r d s 3 t i b7 11 1 1 m a r d s 2 t i b8 11 0 1 m a r d s 1 t i b0 21 9 m a r d s 0 t i b1 21 8 m a r d s
8 ics9248 -81i advance information 0851?08/06/03 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics9248-81i . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics9248-81i. 3. all other clocks continue to run undisturbed. (including sdram outputs).
9 ics9248-81i advance information 0851?08/06/03 sdram_stop# timing diagram sdram_stop# is an sychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. sdram_stop# is synchronized by the ics9248-81i . all other clocks will continue to run while the sdram clocks are disabled. the sdram clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. notes: 1. all timing is referenced to the internal cpu clock. 2. sdram is an asynchronous input and metastable conditions may exist. this signal is synchronized to the sdram clocks inside the ics9248-81i. 3. all other clocks continue to run undisturbed.
10 ics9248 -81i advance information 0851?08/06/03 pci_stop# timing diagram pci_stop# is an synchronous input to the ics9248-81i . it is used to turn off the pciclk (0:4) clocks for low power operation. pci_stop# is synchronized by the ics9248-81i internally. the minimum that the pciclk (0:4) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:4) clocks. pciclk (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:4) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
11 ics9248-81i advance information 0851?08/06/03 the i/o pins designated by (input/output) on the ics9248- 81i serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. shared pin operation - input/output pins fig. 1 figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
12 ics9248 -81i advance information 0851?08/06/03 fig. 2a fig. 2b
13 ics9248-81i advance information 0851?08/06/03 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . 115c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 0.1 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 ma operating i dd3.3op66 c l = 0 pf; select @ 66mhz 60 180 ma supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 66 180 ma power down supply current input frequency f i v dd = 3.3 v; 11 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t cpu-sdram1 v t = 1.5 v 400 500 ps t cpu-pci 1 v t = 1.5 v 13.35 4 ns 1 guaranteed by design, not 100% tested in production. a i dd3.3pd skew 1 c l = 0 pf; with input address to vdd or g 70 600 electrical characteristics - input/supply/common output parameters t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 16 72 ma supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 23 100 ma t cpu-sdram2 v t = 1.5 v; v tl = 1.25 v 200 500 ps t cpu-pci 2 v t = 1.5 v; v tl = 1.25 v 134ns 1 guaranteed by design, not 100% tested in production. skew 1
14 ics9248 -81i advance information 0851?08/06/03 electrical characteristics - cpuclk t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1a i oh = -12.0 ma 2.4 2.6 v output low voltage v ol1a i ol = 12 ma 0.2 0.4 v output high current i oh1a v oh = 2 v -41 -19 ma output low current i ol1a v ol = 0.8 v 19 37 ma rise time t r1a 1 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time t f1a 1 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle d t1a 1 v t = 1.5 v 444956% skew t sk1a 1 v t = 1.5 v 53 175 ps jitter, cycle-to-cycle t j c y c-c y c1a 1 v t = 1.5 v 250 400 ps jitter, one sigma t j 1s1a 1 v t = 1.5 v 40 150 ps jitter, absolute t jabs1a 1 v t = 1.5 v -350 250 +350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpuclk t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1b i oh = -12.0 ma 2 2.3 v output low voltage v ol1b i ol = 12 ma 0.2 0.4 v output high current i oh1b v oh = 1.7 v -41 -19 ma output low current i ol1b v ol = 0.7 v 19 37 ma rise time t r1b 1 v ol = 0.4 v, v oh = 2.0 v 1.25 1.6 ns fall time t f1b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t1b 1 v t = 1.25 v 444856% skew t sk1b 1 v t = 1.25 v 30 175 ps jitter, cycle-to-cycle t j c y c-c y c1b 1 v t = 1.25 v 250 400 ps jitter, one sigma t j 1s1b 1 v t = 1.25 v 40 150 ps jitter, absolute t jabs1b 1 v t = 1.25 v -350 250 +350 ps 1 guaranteed by design, not 100% tested in production.
15 ics9248-81i advance information 0851?08/06/03 electrical characteristics - pciclk t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 i oh = -11 ma 2.4 3.1 v output low voltage v ol2 i ol = 9.4 ma 0.1 0.4 v output high current i oh2 v oh = 2.0 v -62 -22 ma output low current i ol2 v ol = 0.8 v 16 57 ma rise time 1 t r2 v ol = 0.4 v, v oh = 2.4 v 2 2.8 ns fall time 1 t f2 v oh = 2.4 v, v ol = 0.4 v 1.6 2.3 ns duty cycle 1 d t2 v t = 1.5 v 454855% skew 1 t sk2 v t = 1.5 v 380 500 ps jitter, cycle-to-cycle t j c y c-c y c2 v t = 1.25 v 250 500 ps jitter, one sigma 1 t j 1s2 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs2 v t = 1.5 v -350 150 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics -sdram t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -11 ma 2.4 3.1 v output low voltage v ol3 i ol = 9.4 ma 0.1 0.4 v output high current i oh3 v oh = 2.0 v -62 -22 ma output low current i ol3 v ol = 0.8 v 16 57 ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 1.6 2.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 1.6 2.2 ns d t3a v t = 1.5 v; divide by 2 seclects<124mh z 46 52 57 d t3b v t = 1.5 v; divide by 3 seclects 45 50 55 d t3c v t = 1.5 v; selects >= 124mhz 42 48 54 t sk3a v t = 1.5 v; sdram8,9 110 140 t sk3b v t = 1.5 v; all except sdram8 and 9 150 210 t sk3c v t = 1.5 v; all sdrams 250 400 jitter, cycle-to-cycle t j c y c-c y c3 v t = 1.25 v 250 500 ps jitter, one sigma 1 t j 1s3 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs3 v t = 1.5 v -350 150 350 ps 1 guaranteed by design, not 100% tested in production. ps duty cycle 1 skew 1 (window) %
16 ics9248 -81i advance information 0851?08/06/03 electrical characteristics - ref/48mhz/sio t a = -40c - 85c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4 i oh = -12 ma 2.4 2.6 v output low voltage v ol4 i ol = 10 ma 0.3 0.4 v output high current i oh4 v oh = 2.0 v -32 -22 ma output low current i ol4 v ol = 0.8 v 16 25 ma rise time 1 t r4 v ol = 0.4 v, v oh = 2.4 v 2.4 4 ns fall time 1 t f4 v oh = 2.4 v, v ol = 0.4 v 2.3 4 ns duty cycle 1 d t4 v t = 1.5 v 455055% jitter, one sigma 1 t j 1s4 v t = 1.5 v 500 650 ps jitter, absolute 1 t jabs4 v t = 1.5 v -1 1 ns 1 guaranteed by design, not 100% tested in production.
17 ics9248-81i advance information 0851?08/06/03 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and ground traces as wide as the via pad for lower inductance. notes: 1) all clock outputs should have a series terminating resistor, and a 20pf capacitor to ground between the resistor and clock pin. not shown in all places to improve readibility of diagram. 2) optional crystal load capacitors are recommended. they should be included in the layout but not inserted unless needed. connections to vdd: c1 c1 c4 1 clock load c3 c3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 ferrite bead vdd c2 22f/20v tantalum ferrite bead vdd c2 22f/20v tantalum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 = routed power = ground connection key (component side copper) = ground plane connection = power route connection = solder pads = clock load ground 2.5v power route 3.3v power route 3.3v power route
18 ics9248 -81i advance information 0851?08/06/03 ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ordering information ics9248 y fi-81 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp

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